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CAT24WC129
128K-Bit I2C Serial CMOS EEPROM FEATURES
I 1MHz I2C Bus Compatible* I 1.8 to 6 Volt Operation I Low Power CMOS Technology I 64-Byte Page Write Buffer I Self-Timed Write Cycle with Auto-Clear I Commercial, Industrial and Automotive I Write Protect Feature I 100,000 Program/Erase Cycles I 100 Year Data Retention I 8-Pin DIP or 8-Pin SOIC
H
GEN FR ALO
EE
LE
A D F R E ETM
- Top 1/4 Array Protected When WP at VIH
I "Green" Package Options Available
Temperature Ranges
DESCRIPTION
The CAT24WC129 is a 128K-bit Serial CMOS E2PROM internally organized as 16384 words of 8 bits each. Catalyst's advanced CMOS technology substantially
PIN CONFIGURATION
DIP Package (P, L)
NC NC NC VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
SOIC Package (J, W, K, X)
NC NC NC VSS
PIN FUNCTIONS
Pin Name SDA SCL WP VCC VSS
D
is
1 2 3 4 8 7 6 5
o c
VCC WP SCL SDA
i t n
u n
VCC VSS SDA WP
reduces device power requirements. The CAT24WC129 features a 64-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.
BLOCK DIAGRAM
EXTERNAL LOAD
d e
DOUT ACK CONTROL LOGIC
a P
t r
SENSE AMPS SHIFT REGISTERS
WORD ADDRESS BUFFERS
COLUMN DECODERS 512
START/STOP LOGIC
XDEC
256
EEPROM 256X512
Function
DATA IN STORAGE
Serial Data/Address Serial Clock Write Protect +1.8V to +6V Power Supply Ground
SCL STATE COUNTERS
HIGH VOLTAGE/ TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 1079, Rev. V
CAT24WC129
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND TDR
(3) (3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Min. 100,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method
MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008
VZAP(3) ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol ICC1 ICC2 ISB(5) ILI ILO VIL VIH VOL1 VOL2
Parameter Power Supply Current - Read Power Supply Current - Write Standby Current
Input Leakage Current
Output Leakage Current
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN(3) Test Max. 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Input/Output Capacitance (SDA) Input Capacitance (SCL, WP)
D
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = +3.0V) Output Low Voltage (VCC = +1.8V)
is
o c
i t n
Min. -1
u n
Limits Typ. 3 3 0.5
Max. 1
d e
Units mA mA A A A V V V V
MIL-STD-883, Test Method 3015 JEDEC Standard 17
a P
t r
Test Conditions fSCL = 100 KHz VCC=5V fSCL = 100 KHz VCC=5V VIN = GND or VCC VCC=5V VIN = GND to VCC VOUT = GND to VCC
3 1
VCC x 0.3 VCC + 0.5 0.4
VCC x 0.7
IOL = 3.0 mA IOL = 1.5 mA
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) Maximum standby current (ISB ) = 10A for the Automotive and Extended Automotive temperature range.
Doc. No. 1079, Rev. V
2
CAT24WC129
A.C. CHARACTERISTICS VCC = +1.8V to +6V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V Min. FSCL tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR
(1)
Max. 100
Min.
Max. 400
Min.
Max. 1000
Units
Clock Frequency SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time 0.1 4.7 4.0 4.7 4.0 4.0 0
3.5
0.05 1.2 0.6 1.2 0.6 0.6 0
0.9
0.05 0.5
0.55
100
tF(1) tSU:STO tDH tWR
Stop Condition Setup Time Data Out Hold Time Write Cycle Time
Power-Up Timing (1)(2) Symbol tPUR
tPUW
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
FUNCTIONAL DESCRIPTION
The CAT24WC129 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC129 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated.
is D
Power-Up to Read Operation Power-Up to Write Operation
o c
Parameter
i t n
4.7
100
u n
1.0 300 10
100
0.6
d e
0.3 300 10 Max. 1 1
a P
0.25 0.6 0.4 0.25 0 100 0.3 100 0.25 50 10
t r
kHz s s s s s s ns ns s ns s ns ms
50
Units ms ms
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Doc. No. 1079, Rev. V
CAT24WC129
PIN DESCRIPTIONS
SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition
WP: Write Protect
This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the top 1/4 array of memory (locations 3000H to 3FFFH) is write protected. When left floating, memory is unprotected.
The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC129 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition
Figure 1. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHIGH
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
Figure 3. Start/Stop Timing
is D
SDA
SDA SCL
o c
8TH BIT BYTE n
i t n
tHD:DAT tAA
tLOW
u n
tR tSU:DAT tDH
A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
d e
a P
t r
tSU:STO
tBUF
ACK tWR STOP CONDITION START CONDITION ADDRESS
START BIT
STOP BIT
Doc. No. 1079, Rev. V
4
CAT24WC129
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The seven most significant bits of the 8-bit slave address are fixed as 1010XXX (Fig. 5), where X can be a 0 or 1. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC129 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC129 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC129 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte.
knowledge, the CAT24WC129 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
WRITE OPERATIONS
Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24WC129. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24WC129 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write
When the CAT24WC129 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acFigure 4. Acknowledge Timing
is D
SCL FROM MASTER
DATA OUTPUT FROM TRANSMITTER
o c
i t n
1
0 1
u n
The CAT24WC129 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 63 additional bytes. After each byte has been transmitted, CAT24WC129 will respond with an
d e
8
a P
t r
9
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 A2 X A1 X A0 X R/W
X is Don't Care, can be a '0' or a '1'.
5
Doc. No. 1079, Rev. V
CAT24WC129
acknowledge, and internally increment the six low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter `wraps around', and previously transmitted data will be overwritten. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24WC129 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC129 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24WC129 is still busy with the write operation, no ACK will be returned. If CAT24WC129 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
read only. The CAT24WC129 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device's failure to send an acknowledge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24WC129 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read
WRITE PROTECTION
The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the top 1/4 array of memory (locations 3000H to 3FFFH) is protected and becomes Figure 6. Byte Write Timing
S T A R T
BUS ACTIVITY: MASTER
*=Don't Care Bit
Figure 7. Page Write Timing
S T A R T S T O P P A C K A C K A C K A C K A C K A C K
D
S
SDA LINE
is
S
SLAVE ADDRESS
o c
SLAVE ADDRESS
i t n
**
u n
A C K
The CAT24WC129's address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=16383), then the counter will `wrap around' to address 0 and continue to clock out data. After the CAT24WC129 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read
d e
DATA A C K
a P
S T O P P
t r
Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a
BYTE ADDRESS A15-A8 A7-A0
A C K
A C K
BUS ACTIVITY: MASTER SDA LINE
BYTE ADDRESS A15-A8 A7-A0
DATA
DATA n
DATA n+63
**
A C K
*=Don't Care Bit
Doc. No. 1079, Rev. V
6
CAT24WC129
`dummy' write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24WC129 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24WC129 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24WC129 sends the initial 8bit byte requested, the Master will respond with an acknowledge which tells the device it requires more Figure 8. Immediate Address Read Timing
data. The CAT24WC129 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24WC129 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC129 address bits so that the entire memory array can be read during one operation. If more than E (where E=16383) bytes are read out, the counter will `wrap around' and continue to clock out data bytes.
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
SCL
SDA
Figure 9. Selective Read Timing
S T A R T S T A R T S A C K A C K A C K N O A C K S T O P P
BUS ACTIVITY: MASTER
is D
SDA LINE S
o c
A C K
DATA OUT
i t n
8 8TH BIT
u n
DATA A C K 9 NO ACK
d e
S T O P P N O A C K
a P
t r
STOP
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
SLAVE ADDRESS
DATA
**
*=Don't Care Bit
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Doc. No. 1079, Rev. V
CAT24WC129
Figure 10. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K N O A C K SLAVE ADDRESS S T O P P
DATA n
DATA n+1
DATA n+2
DATA n+x
ORDERING INFORMATION
Prefix CAT Device # 24WC129 K Suffix I
Optional Company ID
Product Number
Temperature Range Blank = Commercial (0 - 70C) I = Industrial (-40 - 85C) A = Automotive (-40 - 105C)*
* -40 to +125C is available upon request
Notes: (1) The device used in the above example is a 24WC129KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWA). For additional information, please contact your Catalyst sales office.
is D
o c
Package P: PDIP K: SOIC (EIAJ) J: SOIC (JEDEC) L: PDIP (Lead free, Halogen free) X: SOIC (EIAJ, Lead free, Halogen free) W: SOIC (JEDEC, Lead free, Halogen free)
i t n
u n
d e
-1.8
TE13
a P
t r
Rev A(2)
Tape & Reel
Die Revision
Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V 3: 3.0V - 5.5V
Doc. No. 1079, Rev. V
8
REVISION HISTORY
Date 12/10/2003 04/18/04 Revision Comments C D Eliminated Commercial temperature range Delete data sheet designation Update Features Update Ordering Information Update Rev Letter to T 7/23/04 8/5/04 U V Add die revision to Ordering Information Update DC Operating Characteristics & notes
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM AE2 TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
is D
o c
i t n
u n
d e
a P
t r
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication #: Revison: Issue date:
1079 V 08/05/04

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